USB (Universal Serial Bus) is a communication standard when a high speed communication is carried out between computers by using a serial bus. In recent years, examples increase in which a communication apparatus carrying out the USB communication (hereinafter, to be referred to as a USB communication apparatus) is installed in a mobile apparatus such as a digital camera or PDA (personal Digital Assistant). Such a mobile apparatus receives the supply of power from a battery. For this reason, a demand for a smaller power consumption amount is high in the USB communication apparatus installed in the mobile apparatus.
By the way, in a USB2.0 standard that is mainstream at present, there is a UTMI+(USB2.0 Transceiver Macrocell Interface) standard. The UTMI+ standard is prepared for the purpose of unifying the interfaces of a physical layer (PHY) in the USB communication apparatus based on the USB2.0 standard. However, the UTMI+ standard does not define a technique of reducing the power consumption amount. Because the power consumption amount in a circuit for the physical layer is large, the USB communication apparatus installed in the mobile device is requested to reduce the power consumption amount.
Patent Literature 1 (JP 2006-135397A) discloses a data transfer control apparatus that can save the power of the physical layer circuit. The data transfer control apparatus in Patent Literature 1 will be described below with reference to FIG. 1 to FIG. 3B.
FIG. 1 is a block diagram showing a configuration example of a data transfer control apparatus in Patent Literature 1. The data transfer control apparatus is provided with a transceiver 110, a transfer controller 170 and a data buffer (FIFO) 100.
The transceiver 110 transmits or receives a USB packet by using a differential signal line (of lines DP and DM). The transceiver 110 is provided with a logic circuit 120 as a part of a logical layer circuit of the USB, and an analog front-end circuit 130 as a physical layer circuit. The logic circuit 120 executes processes of generating and removing EOP (End Of Packet), SYNC (SYNChronization) and a line state of a differential signal (J, K, SE0 and so on). The analog front-end circuit 130 includes a transmitting circuit 140 and a receiving circuit 150. The transmitting circuit 140 transmits a packet through the USB bus. Specifically, the transmitting circuit 140 drives the differential signal line of the USB bus by using a current source 142 to be described later and consequently transmits the packet. The receiving circuit 150 receives a packet transferred through the USB bus. Specifically, in the USB bus, the line state of the differential signal line is detected, thereby receiving the packet (serial data).
The transfer controller 170 controls the data transfer through the USB bus. The transfer controller 170 is provided with an SIE (Serial Interface Engine) 180 and a buffer controller 190. The SIE 180 executes a packet process, a transaction process, a suspend resume control process and the like. The SIE 180 is provided with a packet analyzing circuit 182, a transaction controller 184 and a packet generating circuit 186. The packet analyzing circuit 182 analyzes the packet received through the USB bus by the receiving circuit 150. The transaction controller 184 executes the transaction process and instructs a transmission of the packet configuring a transaction. The packet generating circuit 186 generates a packet instructed by the transaction controller 184 and outputs it such that the generated packet is transmitted from the transmitting circuit. The buffer controller 190 executes a region reserving process of a data buffer 100 and an accessing process to the data buffer 100.
The data buffer 100 temporarily stores data transferred through the USB.
Next, FIG. 2 is a block diagram showing the configuration of the transmitting circuit 140 in the data transfer control apparatus in Patent Literature 1. The transmitting circuit 140 is provided with a current source 142, a transmission driver 144 and a transmission control circuit 146.
The current source 142 (constant current source) is placed between a power supply voltage VDD and a first node N1. The transmission driver 144 includes transistors TE1, TE2 and TE3 as shown in FIG. 2. Also, the signal line DP is connected to a termination resistor RP1 on a device side and a termination resistor RP2 on a host side. The signal line DMA is connected to a termination resistor RM1 on the device side and a termination resistor RM2 on the host side. Outputs of the transmission driver 144 are connected to the termination resistors RP1 and RM1. Similarly, outputs of the transmission driver on the host side are connected to the termination resistors RP2 and RM2. The transmission control circuit 146 generates transmission control signals GC1, GC2 and GC3 and outputs to the transmission driver 144.
FIG. 3A shows timing charts in the transmission control signals GC1, GC2 and GC3 generated by the transmission control circuit 146. In the above-mentioned configuration, when the transmission control circuit 146 activates the transmission control signal GC1, so as to turn on the transistor TE1. Then, a current from the current source 142 is supplied through the transistor TE1 to the signal line DP. On the other hand, when the transmission control circuit 146 activates the transmission control signal GC2 so as to turn on the transistor TE2. The current from the current source 142 is supplied through the transistor TE2 to the signal line DM. In a packet transmission period, the transmission control circuit 146 controls the transmission control signals GC1 and GC2 in this way and generates the line state of the differential signal line of the USB bus.
Also, in a period except the packet transmission period, the transmission control circuit 146 activates the transmission control signal GC3 so as to turn on the transistor TE3. Thus, the current from the current source 142 is supplied through the transistor TE3 to the ground GND. In this way, since the current continues to be supplied from the current source 142 to the ground GND even in the period except the packet transmission period, the voltage of the node N1 is made stable. However, since the current continues to be supplied even in the period except the packet transmission period, the power consumption amount of the transmitting circuit 140 becomes great.
For this reason, in the transmission control circuit 146 in Patent Literature 1, the output timing of the transmission control signal is changed. FIG. 3B shows timing charts in the transmission control signals GC1, GC2 and GC3 generated by the transmission control circuit 146. As shown in FIG. 3B, the transmission control circuit 146 activates the transmission control signal GC3 at a timing C2 prior to a timing C1 at which the packet is transmitted onto the USB bus.
By the above-mentioned configuration, the appropriate packet transmission is possible in the packet transmission period by using the current source 142, and a useless current can be prevented from being supplied to the ground GND in the period except the packet transmission period. Also, a length of a transmission waiting period TS between the timings C1 and C2 is set to a length enough to stabilize the current of the current source 142 and the voltage of the node N1. Consequently, as soon as the packet transmission is started, the stable current can be supplied from the current source 142 to the signal lines DP and DM.